The high frequency power amplifier circuit comprises an input circuit receiving an input signal, a first cascode stage connected to the input circuit and a DC voltage source, a second cascode stage supplied by the first cascode stage and receiving the input signal from the first cascode stage, and an output circuit connected to the second cascode stage and outputting an output signal.
Such high frequency power amplifier circuits are, for example, embodied as 20 dB glass A amplifier circuits for operating in a frequency range from 40 MHz to 900 MHz. In such a high frequency power amplifier circuit, the swing at the emitter of the transistor of the second cascode stage rises above the base voltage and causes emitter-base-reverse-break down under high input signal condition, i.e. if the input signal exceeds a certain level. As the emitter voltage at the transistor of the second cascode stage increases further and goes beyond the emitter base break-down voltage, for example 2.5 V, the transistor breaks down, and due to this break down, there is a further bigger increase in the base emitter voltage of the transistor. The increase of emitter voltage and, thereby, the voltage at the related terminal of the transistor in the first cascode stage results in a permanent break down of the transistor in the first cascode stage.
FIG. 1 shows the relevant circuit portion of a high frequency power amplifier circuit including a FET 2 having a source S, a drain D and a gate G and a bipolar transistor 4 having an emitter E, a collector C and a base B. The source of the FET 2 is connected through a resistor 6 to ground 8. The base of the transistor 4 is connected to a DC bias 10. The input signal VIN is supplied to the gate of the FET 2 to the emitter E of the transistor 4. The input signal is also supplied through the drain D of the FET 2 to the emitter E of the transistor 4. The output signal VOUT is output from the collector C of the transistor 4.
FIGS. 2a and 2b show the influence of the level of the input signal to the DC level and the emitter E of the transistor 4. FIG. 2a shows a low level input signal SLOW, and a DC level which is unaffected by the input signal. FIG. 2b shows the case of a high input signal SHIGH having a so-called high swing. Due to distortions coming from the FET of the power supply circuit, the DC voltage and the emitter of the transistor 4 rises to a new DC level. At a certain voltage, the emitter voltage becomes the same as the base voltage, and the transistor 4 will break down and give a very high impedance at the drain of the FET. This will further increase the voltage at the drain of the FET or swing at the transmitter. As the emitter voltage increases further and goes beyond the emitter-base-break down-voltage, the increasing emitter voltage of the transistor and the drain voltage of the FET, respectively, results in a permanent break down of the FET.
In order to verify the above, the behaviour of the high frequency power amplifier circuit under a single tone input signal was studied. FIGS. 3 to 6 show the results of this study, wherein FIGS. 3 to 5 show the base voltage and emitter voltage of the transistor 4 of the second cascode stage versus the level of the input signal and the frequencies of 50 MHz, 550 MHz and 850 MHz input signal frequency. As the single tone input level increases from about 62 dBmV to 64 dBmV, the emitter voltage Ve of the transistor 4 increases while the base voltage Vb decreases. At a particular input level between about 65 dBmV and 68 dBmV which is in the range of the break down voltage of 2,5 V of the transistor 4 is crossed and the transistor 4 breaks without complete failure. This is followed by a steep rise in the base voltage Vb and the emitter voltage VE of the transistor 4. As the emitter voltage VE is also present at the drain of the FET 2, the drain-gate-voltage and the drain-source-voltage of the FET 2 increase and cross the specified maximum limits of the FET 2. Therefore, the FET becomes liable to breakdown.
From FIGS. 3 to 5, it can also be seen that there is a hysteresis effect involved. If the level of the input signal is increased such that the base-emitter-break down-voltage of the transistor 4 is exceeded, there is a change in the transistor 4 which is not reversible if the transistor 4 is left at normal temperature. When the level of the input signal is again decreased, the base voltage and the emitter voltage of the transistor 4 follow the path Vb—a and Ve—a, respectively (see FIGS. 3 to 5), and the levels are considerably lower than the previous levels. In any case, a sudden rise in base voltage and emitter voltage of transistor 4 is seen after 65 dBmV input.
FIG. 6 shows the DC current in relation to the level of the input signal, i.e. the deviation of the new DC level shown in FIG. 2b in relation to the level of the input signal. The DC current rise is maximum for 550 MHz, and for 50 MHz, the DC current decreases with increasing input level. In other words, the increase in the DC current at 550 MHz is most likely to cause a break down of the transistor and, thereby, of the FET. In other words, 550 MHz is the most critical frequency in the frequencies of 50 MHz, 500 MHz, 550 MHz and 850 MHz.